1. Field of the Invention
The present invention relates to a photoelectric conversion device and an image capturing system.
2. Description of the Related Art
MOS photoelectric conversion devices are recently in rapid demand because of their merits such as low power consumption and high output speed. Concerning the photoelectric conversion devices, there is a need to improve the transfer efficiency when transferring charges (signal) accumulated in a photodiode (PD) to a floating diffusion (FD).
Japanese Patent Laid-Open No. 2003-115580 describes an image capturing pixel of a solid-state image sensor in which a transfer facilitation region 140 belonging to the same layer as a charge accumulation layer 112 of a PD 110 is provided under a transfer gate 130 for transferring charges from the PD 110 to an FD 120 (FIG. 1 of Japanese Patent Laid-Open No. 2003-115580). A method of forming the transfer facilitation region 140 is shown in FIGS. 4A to 4C of Japanese Patent Laid-Open No. 2003-115580. In the step shown in FIG. 4A of Japanese Patent Laid-Open No. 2003-115580, n-type ions and p-type ions are sequentially implanted into the entire pixel region using a LOCOS layer 210 as a mask. The transfer facilitation region 140 and a dark current suppression layer 170 are thus formed sequentially in the entire pixel region. In the step shown in FIG. 4B of Japanese Patent Laid-Open No. 2003-115580, after forming a gate electrode film 131, n-type ions and p-type ions are sequentially implanted using the gate electrode film 131 and a resist film 230 as a mask. The charge accumulation layer 112 and a photoelectric conversion region 111 of the PD 110 are thus sequentially formed, and simultaneously, the boundaries of the dark current suppression layer 170 and the transfer facilitation region 140 on the side of the PD 110 are formed in a self-aligned manner. In the step shown in FIG. 4C of Japanese Patent Laid-Open No. 2003-115580, n-type ions are implanted using the gate electrode film 131 and a resist film 240 as a mask. The FD 120 is thus formed, and simultaneously, the boundaries of the dark current suppression layer 170 and the transfer facilitation region 140 on the side of the FD 120 are formed in a self-aligned manner. That is, the signal charge transfer facilitation region is formed in a self-aligned matter under the transfer gate. According to Japanese Patent Laid-Open No. 2003-115580, since the transfer facilitation region and the transfer gate can sufficiently overlap, it is supposed to be possible to effectively improve the transfer characteristic of the transfer gate section.
On the other hand, there is a need to reduce noise generated by a dark current in the photoelectric conversion device. Japanese Patent Laid-Open No. 2003-258229 describes providing dark current reduction regions 701 and 702 containing a p-type impurity between an isolation insulating film 104 and a photodiode 201 (n-type semiconductor region 103 and p+-layer 801) (FIGS. 7 and 8 of Japanese Patent Laid-Open No. 2003-258229). Since this structure can reduce the amount of minority carrier (electrons) which is generated immediately under an interconnection layer 105 and diffused to the photodiode 201, it is supposed to be possible to reduce the dark current of the photodiode 201. Japanese Patent Laid-Open No. 2000-353801 describes a solid-state image sensor structure in which a p+-impurity region 1a extends from an end portion E of an isolation insulating layer 3 to the side of the formation region of a transfer switch M1 in a semiconductor substrate 2 under a gate electrode layer 8a of the transfer switch M1 (FIG. 1 of Japanese Patent Laid-Open No. 2000-353801). A method of forming the p+-impurity region 1a is shown in FIGS. 7 to 9 of Japanese Patent Laid-Open No. 2000-353801. In the step shown in FIG. 7 of Japanese Patent Laid-Open No. 2000-353801, a silicon nitride film 12 is patterned using a resist pattern 13 as a mask. In the step shown in FIG. 8 of Japanese Patent Laid-Open No. 2000-353801, boron (B) ions are obliquely implanted without removing the resist pattern 13. This enables to implant boron up to the lower region of the patterned silicon nitride film 12. In the step shown in FIG. 9 of Japanese Patent Laid-Open No. 2000-353801, the resist pattern 13 is removed, and thermal oxidation is performed. The isolation insulating layer 3 and the p+-impurity region 1a are thus formed. According to Japanese Patent Laid-Open No. 2000-353801, since the p+-impurity region 1a prevents a depletion layer 50 extending from the p-n junction from reaching the end portion E of the isolation insulating layer 3 (FIG. 10 of Japanese Patent Laid-Open No. 2000-353801), it is supposed to be possible to suppress dark current generation in the transfer transistor section.
The technique described in Japanese Patent Laid-Open No. 2003-115580 forms the transfer facilitation region 140 using the LOCOS layer 210 as a mask. For this reason, the transfer facilitation region 140 is considered to be in contact with the LOCOS layer 210 in the direction of channel width of the transfer gate 130. When the transfer facilitation region 140 is in contact with the LOCOS layer 210, the depletion layer end reaches the interface between the transfer facilitation region 140 and the LOCOS layer 210 upon transferring charges from the charge accumulation layer 112 of the PD 110 to the FD 120. When the depletion layer end reaches the interface of the LOCOS layer 210, a large dark current is generated due to the level of the interface. For this reason, noise caused by the dark current generated due to the level of the interface of the LOCOS layer (isolation portion) 210 mixes with a signal corresponding to the charges transferred from the PD (photoelectric converter) 110 to the FD section (charge voltage converter) 120.
On the other hand, Japanese Patent Laid-Open No. 2003-258229 makes no mention of what kind of semiconductor region should be provided under the gate of the transfer MOS transistor. Japanese Patent Laid-Open No. 2000-353801 makes no mention of how to improve the efficiency of charge transfer from the PD region to the FD region.